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Development of cost-effective high-density through-wafer interconnects for 3D microsystems

Abstract

High-density through-wafer interconnects are of great interest for fabricating real 3D microsystems. A complete solution for realizing through-wafer interconnects is presented. The proposed solution is believed to be cost effective and easy to integrate in a device process flow. A deep reactive ion etch process was developed to etch 20 × 20 µm2 via holes through 300 µm thick silicon wafers. Thermal oxide is used to insulate the vias from the bulk silicon and heavily doped polysilicon is used as the conductor. Aluminum metallization is provided on both sides of the wafer. The electrical resistance of a single through-wafer via is close to 30 Ω.

Category

Academic article

Language

English

Author(s)

Affiliation

  • SINTEF Digital / Smart Sensors and Microsystems

Year

2006

Published in

Journal of Micromechanics and Microengineering (JMM)

ISSN

0960-1317

Publisher

IOP Publishing

Volume

16

Issue

6 Spesial Issue

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